1. Field of the Invention
The present invention relates to a method of forming a multilayer interconnection structure, and a manufacturing method for multilayer wiring boards, and more specifically, relates to a contact hole formation technique for connecting between wiring layers.
2. Description of the Related Art
Recently, in electronic devices such as semiconductor devices and electro-optic devices, wiring is formed in multi layers in order to increase the degree of integration. In devices having such a multi-layer wiring structure, a contact hole (opening) is formed in an interlayer insulating film, in order to secure conduction between wiring layers laminated via the interlayer insulating film.
For example, in a field of electro-optic devices, one in which TFTs for pixel switching, data lines, and pixel electrodes are formed in multi layers has been developed (see Japanese Patent No. 2625268). In devices having such a structure, for example, TFTs are arranged on the bottom layer of the substrate, and data lines are arranged thereon via the first interlayer insulating film. The second interlayer insulating film is provided on the substrate so as to cover the data lines and the first interlayer insulating film, and pixel electrodes are arranged thereon. In order to secure conduction between these layers, the source region of the TFT is connected to the data line via a first contact hole penetrating the gate insulator and the first interlayer insulating film, and the drain region is connected to the pixel electrode via a second contact hole penetrating the gate insulator, the first interlayer insulating film and the second interlayer insulating film.
Conventionally, dry etching has been used for the step of forming such an opening.
However, when the contact hole is formed by etching, the obtained devices may have a difference in electric characteristics according to ununiformity in film thickness of the interlayer insulating film in which the contact hole is formed. For example, since over etching occurs in a portion where the film thickness is thin, the shape of the contact hole may be enlarged, or the wiring layer on the lower layer side may be made thin. Particularly in the case of dry etching, since the etching selection ratio between the insulating material and the conductive material cannot be sufficiently ensured, the degree of thinning of the film increases. Such thinning of the wiring layer on the lower layer side causes an increase in contact resistance or non-ohmic conduction characteristics, and sometimes causes insufficient conduction. The enlarged shape of the contact hole due to over etching causes an increase in leak current between adjacent conductive layers or a short circuit failure. The problem of leak current or short circuit becomes serious as the density of the wiring layer increases and the gaps between the adjacent wiring layers becomes narrower.
Moreover, in a portion where the film thickness is thick, the interlayer insulating film remains at the bottom of the contact hole due to insufficient etching, thereby causing insufficient conduction. In the step of etching described above, plasma etching is often performed, but in this case, plasma damage may occur in the substrate, thereby deteriorating the electric characteristics of the device. Furthermore, since a reaction product is generated in the plasma etching, the product adheres to the bottom and the side wall of the contact hole, thereby causing insufficient conduction.
In a device having the multilayer structure described above, as the gap between the wiring layers to be connected in the vertical direction increases (that is, the number of interlayer insulating films arranged between the layers increases, or the film thickness increases), the aspect ratio of the contact holes arranged between these increases, and hence it becomes difficult to form the opening with one step. Conventionally, therefore, a method has been employed where a relay electrode is provided between these wiring layers, so as to connect between the wiring layer on the lower layer side and the relay electrode, and between the relay electrode and the wiring layer on the upper layer side with separate contact holes (see Japanese Patent No. 2625268). However, with this method, since the relay electrode is formed, the degree of integration decreases, thereby preventing high performance of the device.